1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device having a redundant memory cell array.
2. Description of the Related Art
FIG. 1 is a block diagram of a conventional semiconductor memory device having a redundant memory cell array 108. In FIG. 1, a row address buffer 101 latches an n-bit row address RA that is input to the semiconductor memory device by an external device when a row address strobe signal RASB, that is buffered by a row address strobe buffer 110, is strobed by the external device. The row address strobe buffer 110 is synchronized with a system clock to buffer the externally applied row address strobe signal RASB. A control signal generator 109 delays the buffered RASB signal output from the row address strobe buffer 110 by a predetermined period of time in order to generate a delayed row address strobe signal RASBD.
A normal memory cell array 106 is composed of a plurality of memory cells arranged in a matrix pattern. Each memory cell can be accessed by the combination of a normal word line and a bit line. Where the row address RA is composed of n bits, the number of individually driven normal word lines included in the memory cell array 106 should be less than 2.sup.n. Each one of the normal word lines included in the memory cell array 106 is selectively activated by a corresponding value of the row address RA.
Row address decoding is performed in order to select one of the word lines of normal memory cell array 106. The row address decoding related to the normal memory cell array 106 is performed by a row predecoder 102 and a row decoder 105. Here, the row predecoder 102 receives (n-k) bits of the n row address bits output by row address buffer 101 while the remaining k bits are passed through to row decoder 105. The row predecoder 102 decodes the (n-k) bits of the row address and outputs the result as predecoder row address signal PRA, which is composed of 2.sup.(n-k) signals. The signal PRA and the remaining k bits of row address RA are applied to the row decoder 105. The row decoder 105 includes 2.sup.(n-k) k-bit decoders which each decode the remaining k bits and control a corresponding one of 2.sup.(n-k) normal word line drivers. The 2.sup.(n-k) k-bit decoders are enabled by the PRA signal output by the row predecoder 102. Thus, the row address decoding function is performed by the row predecoder 102 along with the k-bit decoders included in row decoder 105. The normal word line drivers included in the row decoder 105 are enabled or disabled in response to the signal PRRE output by row decoder disable signal generator 103 and the control signal RASBD and, responsive to the decoded row address RA, drive one of the 2.sup.n normal word lines of the normal memory cell array 106 which are coupled to the row decoder 106.
The memory device of FIG. 1 also includes redundant memory cell array 108 which is used to replace defective memory cells which may occur in the normal memory cell array 106. Each memory cell included in the redundant memory cell array 108 is accessible through the combination of a redundant word line and a bit line.
The size of the redundant memory cell array 108 is determined during design thereof based upon the probability that defects will be generated during the manufacturing process. A row address for driving each redundant word line is not determined during the design of the memory device but during a repair phase after the memory device has been fabricated. The row address decoding for the redundant memory cell array 108 is performed by a redundant row fuse decoder 104 and a redundant row decoder 107. The redundant row fuse decoder 104 receives m bits of the row address output from the row address buffer 101, while the remaining (n-m) bits of the row address RA are passed through to the redundant row decoder 107.
Referring to FIG. 2, the redundant row fuse decoder 104 is composed of a plurality of m-bit address fuse portions 121, 122 and 123. The ellipses in the drawing indicate that more m bit address fuse portions can be included in a particular circuit design. The m-bit address fuse portions 121, 122 and 123 each decode m bits of a row address corresponding to word line in the normal memory cell array 106 that contains a defective memory cell. For example, when the row address RA that specifies a normal word line in the normal memory cell array 106 is composed of 11 bits, the number of bits m decoded in each address fuse portion is 7. Thus, when the row address corresponding to a word line containing a defective memory cell (which are hereinafter referred to as defective row addresses) is 10010111000, then the m-bit address fuse portion is coded using the lower 7 bits, i.e. 0111000.
The coding of the defective row addresses is performed by selectively shorting the fuse array in one of the m bit address fuse circuits 121, 122 or 123 to decode the selected defective address. In such a scheme, all the word lines in the normal memory cell array 106 having the same value for the upper (n-m) bits of the row address are grouped together. Only the defective memory cells within a group can be repaired. For example, when n=11 there are 2.sup.11 normal word lines which can be divided into 24 groups according to the row addresses thereof. Namely, the row address RA can be classified into the groups (00000000000)-(00001111111), (00010000000)-(00011111111), (00100000000)-(00101111111), (00110000000)-(00111111111), . . . , (11110000000)-(11111111111).
Groups which do not have a corresponding m bit address fuse portion 121, 122 or 123 cannot be repaired. For example, if the group in which the upper 4 bits of the row address is (1001) is not assigned an m bit address fuse portion, then defects occurring in the word lines of the normal memory cell array 106 in which the row address of the upper 4 bits is (1001) cannot be repaired.
Furthermore, each m bit address fuse portion 121, 122 and 123 can only decode one word line in a group. Thus, if defects occur in two memory cells in the same normal word line, the two defective memory cells can both be repaired. However, if defects occur in two different word lines in the same group, then both the defective word lines cannot be replaced. For example, if a defective memory cell occurs in the word line with the row address (10010111000) and another defective memory cell occurs in the word line with the row address (10010100110), then only one of the defective cells can be replaced. In this scheme, defective memory cells can occur that may not be replaced even though a usable redundant memory cell in redundant memory cell array 108 exists.
In FIG. 2, the outputs RED1, RED2, . . . , REDi of m-bit address fuse portions 121, 122 and 123 are activated responsive to an m bit defective row address of the row address signal RA that has been coded into the fuse portion. An (n-m)-bit decoder 130 included in the redundant row decoder 107 decodes the remaining higher order (n-m) bits of the row addresses RA and outputs a signal responsive to each group of (n-m) bits in the row address signal RA. Logic gates 141, 142 and 143 combine the output signals from the (n-m) bit decoder 130 with the output of each of the m-bit address fuse portions 121, 122 and 123. More specifically, the logic gate 141 combines the first output of the (n-m)-bit decoder 130 and the RED1 signal and generates an output signal when both inputs are active. Similarly, logic gate 142 combines the second output of the (n-m)-bit decoder 130 and the RED2 signal. And logic gate 143 combines the last output of the (n-m)-bit decoder 130 and the REDi signal. Thus, for example, the logic gate 141 is activated when the upper 4-bits of the row address signal RA is (0000) and RED1 is active, the logic gate 142 is activated when the upper 4-bits of the row address signal RA is (0001) and RED2 is active, and the logic gate 143 is activated when the upper 4-bits of the row address signal RA is (1111) and the REDi is active.
Logic gates 151, 152 and 153 transmit the outputs of the logic gates 141, 142 and 143, respectively, to the corresponding redundant word line drivers 161, 162 and 163, respectively, when the delayed row address strobe signal RASBD is active. Redundant word line drivers 161, 162 and 163 output signals which drive the corresponding redundant word lines R-WL(1), R-WL(2), . . . , R-WL(I), respectively, when the corresponding output signal from one of logic gates 141, 142 or 143 is active.
Returning to FIG. 1, a column address strobe buffer 111 receives a column address strobe signal CASB in synchronization with the system clock. A column address buffer 113 latches an externally input column address signal CA when strobed by the column address strobe signal CASB. A column decoder 112 decodes the column address CA and generates a column line select signal which enables the column select line corresponding to the value of the column address signal CA.
The row decoder disable signal generator 103 generates the row decoder disable signal PRRE which is activated when one of the outputs of the redundant row fuse decoder 104 is active. The row decoder 105 is disabled so that it does not perform a decoding operation when the row decoder disable signal PRRE is active.
The conventional semiconductor memory device described above suffers from the problem that a defective memory cell in normal memory cell array 106 cannot be replaced even though a replacement cell in redundant memory cell array 108 is available because more than one row has a defective memory cell within the same group. The memory device above also runs into problems with slower operating speed and increased chip layout area require for the circuit design.